The present invention relates to a level shift circuit, and particularly to a level shift circuit that converts a signal having a first amplitude to a signal having a second amplitude.
With a recent demand for a reduction in power consumption, a power supply voltage used inside a semiconductor integrated circuit has been gradually reduced. On the other hand, however, there is a case in, which a semiconductor integrated circuit device operated at a high voltage is connected to the outside of a semiconductor integrated circuit operated at a low voltage. In such a case, there is a need to step up or boost a signal of the low voltage-operated semiconductor integrated circuit by a level shift circuit and supply the signal to the external semiconductor integrated circuit device.
The level shift circuit comprises, for example, a flip-flop driven by a high voltage VCC on the output side thereof and an inverting transistor driven by a low voltage VDD on the input side thereof and for inverting the state of the flip-flop. When the difference between VCC and VDD is large where the state of the flip-flop is pulled down from the power supply level VCC to a ground level VSS by the inverting transistor in such a level shift circuit, the force of trying to pull up the state to VCC by the flip-flop becomes strong and the force of trying to pull down it to VSS by the inverting transistor in reverse become weak, so that the state cannot be inverted. Such conditions are apt to take place as the difference between VCC and VDD becomes large, and is prone to occur even when VDD is close to the threshold voltage of the inverting transistor.
In order to prevent such conditions, there is a need to enlarge a gate width of the inverting transistor. Since, however, a current driving capacity of a transistor of the flip-flop looks larger than that of the inverting transistor where the difference between VCC and VDD is large, there is a need to drastically enlarge the gate width of the inverting transistor in order to overcome such a current driving capacity. With the increase in the gate width of the inverting transistor, there is further a need to scale up even a driver circuit for driving the inverting transistor. Thus, there is a fear that a circuit area will greatly increase.
As conventional level shift circuits, there are known those described in, for example, patent documents 1 through 3 shown below. The level shift circuit described in the patent document 1 is configured such that CMOS transistors are two-stage connected in cascade, and a ground level of the CMOS transistor corresponding to the first stage is set to a negative voltage to reduce its threshold voltage, thereby making it possible to invert the CMOS transistor corresponding to the second stage at high speed. The patent document 2 describes a level shift circuit with a state holding function. The present level shift circuit is configured in such a manner that in a flip-flop circuit in which CMOS transistors are connected in ring form, two input signals are respectively inputted from the power supply sides of respective inverters and an output signal is fetched from a connecting portion of the CMOS transistors provided on the side opposite to the CMOS transistors respectively inputted with the input signals. Further, a current driving capacity of the transistor on the ground side in the respective CMOS transistors is set sufficiently smaller than that of the transistor thereof on the power supply side to thereby reduce consumption of a DC current with a level shift. The patent document 3 describes a level shift circuit with a state holding function. The present level shift circuit is configured such that inverters comprised of CMOS transistors are two-stage connected in cascade and a latch transistor driven by a clock signal is inserted at the CMOS transistor corresponding-to the second stage to latch the output of the corresponding inverter.
Japanese Patent Application Laid-Open No. Hei 10(1998)-84259 (3rd to 6th pages and FIGS. 1 and 3).
Japanese Patent Application Laid-Open No. Hei 5(1993)-55900 (2nd to 3rd pages and FIGS. 1 and 6)
Japanese Patent Application Laid-Open No. Hei 9(1997)-244585 (3rd to 12th pages and FIG. 1)
The level shift circuit described in the patent document 1 has the fear that a power supply circuit for generating the negative voltage of the ground level of the CMOS transistor corresponding to the first stage is extra required, thus causing scale-up of a circuit area. Also the patent document 1 does not describe the level shift circuit with the state holding function.
The level shift circuit described in the patent document 2 has the fear that while the consumption of the DC current can be suppressed because the current driving capacity of the transistor on the ground side is set sufficiently smaller than the current driving capacity of the transistor on the power supply side, the time required to invert an output state to an L level becomes long, thereby interfering with its speeding-up. The patent document 2 does not describe a reduction in circuit area where the difference between the voltage on the input side and the voltage on the output side becomes large.
The level shift circuit described in the patent document 3 has the fear that there is a need to input the clock signal in order to latch the output state, and a wiring for input of the clock signal is extra needed, thereby scaling up a circuit area.